FPGA Interconnect Topologies Exploration
FPGA Interconnect Topologies Exploration
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FPGA 互连拓扑探索
DOI：
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发表时间：
2009
期刊：
影响因子：
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通讯作者：
H. Mehrez
中科院分区：
文献类型：
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作者：
Z. Marrakchi;H. Mrabet;Umer Farooq;H. Mehrez
本文提出了一种改进的基于树的FPGA架构的互连网络，它统一了两个单向可编程网络。开发了新的工具来放置和布线最大的基准电路，其中使用不同的优化技术来获得优化的架构。分析了查找表和簇大小的变化对树型结构的面积、性能和功耗的影响。实验结果表明，LUT大小和数组大小为4的架构在面积和静态功耗方面最有效，而LUT和簇大小更大的架构在性能方面更有效。我们还表明，统一的网格与此树拓扑结构导致一个架构，具有良好的布局可扩展性和更好的互连效率相比，VPR风格的网格。
This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most ef-ficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are effi-cient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR-style Mesh.