An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs
复制标题
可变延迟设计性能优化的有效机制
DOI：
10.1145/1278480.1278721
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
M. Marek
中科院分区：
文献类型：
--
作者：
Yu;Da;Shih;M. Marek
在许多设计中，最糟糕的路径可能永远不会被锻炼或不经常锻炼。对于这些设计，在最坏情况下优化电路的策略可能导致资源使用效率低下。通过引入可变延迟，可以改善此类电路的吞吐量。可变延迟设计样式的现有实现之一是基于望远镜单元。伸缩单元中持有逻辑的设计影响电路的吞吐量。在本文中，我们表明传统设计的伸缩单元中的持有逻辑可能不准确。我们利用短路径激活条件比望远镜单元中常用的逻辑更准确。平均而言，我们的方法的性能增长为25.79％，而14.04％，这是在先前的工作中报道的。
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case conditions could lead to inefficient resource use. It is possible to improve the throughput of such circuits by introducing variable latency. One of the existing realizations of variable-latency design style is based on telescopic units. The design of the hold logic in telescopic units influences the circuit's throughput. In this paper, we show that the traditionally-designed hold logic in telescopic units may be inaccurate. We make use of the short path activation conditions to obtain more accurate hold logic than that commonly applied in the telescopic units. On average, our approach achieves a performance gain of 25.79% compared to 14.04%, which was reported in the previous works.