A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
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DOI：
10.1109/jssc.2012.2185340
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发表时间：
2011-06
影响因子：
5.4
通讯作者：
Y. Ikenaga;M. Nomura;Shuji Suenaga;H. Sonohara;Yoshitaka Horikoshi;Toshiyuki Saito;Yukio Ohdaira;Yoichiro Nishio;Tomohiro Iwashita;Miyuki Satou;Koji Nishida;K. Nose;K. Noguchi;Y. Hayashi;M. Mizuno
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文献类型：
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作者：
Y. Ikenaga;M. Nomura;Shuji Suenaga;H. Sonohara;Yoshitaka Horikoshi;Toshiyuki Saito;Yukio Ohdaira;Yoichiro Nishio;Tomohiro Iwashita;Miyuki Satou;Koji Nishida;K. Nose;K. Noguchi;Y. Hayashi;M. Mizuno
超大尺寸soc的AVS技术得到了发展。为了降低设计成本，我们开发了一种采用通用延迟线（UDL）而不是复制延迟线来监测关键路径延迟（TCRIT）的电源电压控制方案。UDL可以在任何产品中使用，而无需进行任何定制。此外，在一个芯片中平均分布4个间距为3mm的监视器的结果可以将由于芯片内变化而产生的误差减少一半。使用这些技术，即使使用简单的监视器设计，所提出的方案与使用单个关键路径副本作为延迟监视器的传统方案相比，产生的错误与TCRIT相当或更小。我们已经证明，使用我们的AVS的40纳米CMOS soc可以将有功功率降低27%。
AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.