Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs
Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs
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DOI：
10.1109/tns.2010.2045901
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发表时间：
2010-06-01
影响因子：
1.8
通讯作者：
Wu, Jinyuan
中科院分区：
文献类型：
--
作者：
Wu, Jinyuan
本文讨论了一种新的FPGA TDC方案--Wave Union TDC的实现，该方案利用多个测量值来提高时间测量精度，沿着讨论了基于FPGA延迟线的TDC中的其他几个问题。FPGA的具体问题，如考虑在不同的FPGA家庭和编码逻辑的延迟线的选择。接下来，讨论了FPGA TDC和ASIC TDC的共同问题，例如粗时间计数器实现方案、逐仓校准和由于单端信号引起的噪声问题。在该文档中描述了用于各种处理阶段的几种资源/功率节省设计方法。
This paper discusses implementation of the Wave Union TDC, a novel scheme of FPGA TDC to improve time measurement precision using multiple measurements, along with several other topics in FPGA delay line based TDCs. FPGA specific issues such as considerations on the delay line choice in different FPGA families and encoding logic are first examined. Next, common problems for both FPGA TDCs and ASIC TDCs such as schemes of coarse time counter implementation, bin-by-bin calibration and noise issues due to single ended signals are discussed. Several resource/power saving design approaches for various processing stages are described in the document.