Clock mesh synthesis with gated local trees and activity driven register clustering
Clock mesh synthesis with gated local trees and activity driven register clustering
复制标题
具有门控本地树和活动驱动寄存器集群的时钟网格综合
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
B. Taskin
中科院分区：
文献类型：
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作者：
Jianchao Lu;Xiaomi Mao;B. Taskin
提出了一种时钟网格网络综合方法，在局部子树上实现时钟门控，以降低时钟功耗。时钟门控是用寄存器集群策略来执行的，该寄存器集群策略考虑i）局部区域中寄存器之间的切换活动的相似性和ii）设计中每个局部数据路径上的定时松弛。这是文献中已知的第一项工作，它封装了门控本地树和活动驱动寄存器集群的有效实现，具有用于时钟网格合成的定时松弛意识。实验结果表明，采用门控局部树和活动驱动的寄存器分簇，可以在有限的偏斜恶化的情况下，将网状网络上的开关电容减少22%。该方法具有低功耗和高性能两种综合模式，以满足不同的设计目的。
A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known in literature that encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. Experimental results show that with gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The proposed method has two synthesis modes as low power mode and high performance mode to serve different design purposes.