Design of an Improved CMOS Phase/Frequency Detector
Design of an Improved CMOS Phase/Frequency Detector
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DOI：
10.1007/s00034-005-0819-y
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发表时间：
2006-08
期刊：
影响因子：
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通讯作者：
R. Y. Chen;Hong-Yu Huang;Ming-Yu Hsieh
中科院分区：
文献类型：
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作者：
R. Y. Chen;Hong-Yu Huang;Ming-Yu Hsieh
提出了一种互补金属氧化物半导体（CMOS）鉴频鉴相器（PFD）。介绍了一种改进的CMOS D型主从触发器，并将其应用于PFD中。更高的速度和更低的功率操作归因于减少的节点电容。 电荷共享现象被规避在建议的触发器和PFD。 分析研究了PFD的最大工作频率。基于一阶近似，为PFD的设备尺寸方程推导。所提出的PFD在高工作频率下的相位和频率灵敏度都有所改善。HSPICE仿真表明，采用改进的PFD的锁相环（PLL）的频率捕获速度更快。PLL仿真也验证了PFD的最大工作频率与我们的分析结果一致。
A complementary metal oxide semiconductor (CMOS) phase/frequency detector (PFD) is presented. An improved CMOS D-type master-slave flip-flop is described and adopted in the PFD. Higher speed and lower power operation is attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed flip-flop and PFD. The maximum frequency of operation of the PFD is analytically studied. Device-sizing equations, based upon a first-order approximation, for the PFD are derived. The proposed PFD shows improvements in both phase and frequency sensitivities at high operating frequencies. HSPICE simulations of a phase-locked loop (PLL) employing the improved PFD demonstrate a faster frequency acquisition. The PLL simulations also verify that the maximum operating frequency of the PFD is in agreement with our analytical results.