FPGA Design of an Open-Loop True Random Number Generator
FPGA Design of an Open-Loop True Random Number Generator
复制标题
开环真随机数发生器的 FPGA 设计
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
J. Danger
中科院分区：
文献类型：
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作者：
Florent Lozach;M. Ben;T. Graba;J. Danger
提出了一种基于Xilinx的亚稳态真随机数产生器的设计方法。由于它的结构是基于开环延迟链的，因此它对耦合攻击不像基于振荡器的TRNG那样敏感，从而提供了高吞吐量和抗物理攻击的安全性。该结构在Virtex-5 XC5VLX50T上实现，占用了4%的可用资源，并以20~Mbps的速率产生随机比特。这项工作给出了详细的设计方法，更具体地说，TRNG结构的布局、布线和定时分析。此外，这个TRNG的随机性质量已经使用AIS-31和NIST统计测试进行了验证。
This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the available resources and generates random bits at a 20~Mbps rate. This work gives a detailed description of the design methodology, more specifically the placement, routing and timing analysis of the TRNG structure. Also, the randomness quality of this TRNG has been validated using AIS-31 and NIST statistical tests.