Path confidence based lookahead prefetching

Path confidence based lookahead prefetching
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DOI:
10.1109/micro.2016.7783763
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发表时间:
2016-10
期刊:
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
影响因子:
--
通讯作者:
Jinchun Kim;Seth H. Pugsley;Paul V. Gratz;A. Reddy;C. Wilkerson;Zeshan A. Chishti
Jinchun Kim;Seth H. Pugsley;Paul V. Gratz;A. Reddy;C. Wilkerson;Zeshan A. Chishti
中科院分区:
其他
文献类型:
--
作者:
Jinchun Kim;Seth H. Pugsley;Paul V. Gratz;A. Reddy;C. Wilkerson;Zeshan A. Chishti

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设计预防器以最大程度地提高系统性能通常需要在覆盖范围和准确性之间取得微妙的平衡。在具有复杂地址模式的工作负载中,实现高覆盖范围和准确性尤其具有挑战性,这可能需要大量的历史记录才能准确预测未来的地址。本文介绍了签名路径Prefetcher(SPP),该路径为预摘要设计中的三个经典挑战提供了有效的解决方案。首先,SPP使用基于压缩历史的方案,该方案可以准确预测复杂的地址模式。其次,与其他基于历史记录的算法不同,当地址模式在物理页面之间过渡时,它会错过许多预取机会,而SPP在物理页面边界上跟踪复杂的模式,并在转到新页面后继续进行预取。最后,SPP利用其对预测的信心,以每次回复流的基础自适应节气门自身。在我们的分析中,我们发现SPP在无预辩的基线上提高了27.2%的绩效,并优于最先进的最佳偏移预定器6.4%。 SPP以最小的开销来完成此操作,严格在物理地址空间中运行,而无需任何其他处理器核心状态,例如PC。
Designing prefetchers to maximize system performance often requires a delicate balance between coverage and accuracy. Achieving both high coverage and accuracy is particularly challenging in workloads with complex address patterns, which may require large amounts of history to accurately predict future addresses. This paper describes the Signature Path Prefetcher (SPP), which offers effective solutions for three classic challenges in prefetcher design. First, SPP uses a compressed history based scheme that accurately predicts complex address patterns. Second, unlike other history based algorithms, which miss out on many prefetching opportunities when address patterns make a transition between physical pages, SPP tracks complex patterns across physical page boundaries and continues prefetching as soon as they move to new pages. Finally, SPP uses the confidence it has in its predictions to adaptively throttle itself on a per-prefetch stream basis. In our analysis, we find that SPP improves performance by 27.2% over a no-prefetching baseline, and outperforms the state-of-the-art Best Offset prefetcher by 6.4%. SPP does this with minimal overhead, operating strictly in the physical address space, and without requiring any additional processor core state, such as the PC.