Sine/cos generator for direct digital frequency synthesizer using pipelined CORDIC processor
Sine/cos generator for direct digital frequency synthesizer using pipelined CORDIC processor
复制标题
使用流水线 CORDIC 处理器的直接数字频率合成器的正弦/余弦发生器
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
S. Ramasamy
中科院分区：
文献类型：
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作者：
P. Saravanan;S. Ramasamy
信号发生器，也称为函数发生器，它们是产生模拟或数字形式的重复或非重复电子信号的电子设备。它们通常用于设计、测试、故障排除和修理电子或电声设备，尽管它们也经常具有艺术用途。函数发生器中添加的许多功能使其设计变得复杂并增加了成本。我们无法创建任何任意波形。有机会使用直接数字频率合成（DDFS）对熟悉的函数发生器进行彻底的重新设计。在本文中，我们提出了一种使用 CORDIC 算法计算 DDFS 的正弦和余弦函数的硬件高效架构。该方法使用 ModelSim 仿真软件进行仿真，并使用 Xilinx ISE 设计套件进行综合，并且所提出的架构在 Xilinx FPGA 目标器件（即 SPARTAN 3E）上实现。最后，提出了器件利用率总结和时序报告，最后我们使用 Synopsys 工具修改了 180 nm 标准 CMOS 技术中的 CORDIC 算法实现，并研究了其性能。对 ASIC 有利的主要因素是其较低的功耗，这是 DDFS 器件的首要关注点及其大批量的较低成本。所提出的架构已采用0.18微米技术在VLSI中实现，核心面积为7.452 mm2，芯片尺寸为3.16 mm × 3.16 mm。
Signal generators, also known as function generators, they are electronic devices that generate repeating or non-repeating electronic signals in either the analog or digital form. They are generally used in designing, testing, troubleshooting, and repairing electronic or electro acoustic devices, though they often have artistic uses as well. Many features added to function generators have complicated their design and increased their cost. We cannot create any arbitrary waveform. There is an opportunity for a radical redesign of the familiar function generator using Direct Digital Frequency Synthesis (DDFS). In this paper we present a hardware efficient architecture by using CORDIC algorithm for the calculation of sine and cosine functions for DDFS. This approach is simulated using ModelSim simulation software, synthesized using Xilinx ISE design suite and the proposed architecture is implemented on Xilinx FPGA target device i.e. SPARTAN 3E. Finally, the device utilization summary and timing reports are presented, finally we revised CORDIC algorithm implementation in 180 nm standard CMOS technology using Synopsys tools and investigate its performance The dominant factor favourable to ASICs is their lower power consumption, which is of primary concern for DDFS devices and their lower cost in large volumes. The proposed architecture has been implemented in VLSI using 0.18 micron technology with a core area of 7.452 mm2, and the dimensions of the chip are 3.16 mm 3.16 mm.