Hybrid cache architecture for high speed packet processing
Hybrid cache architecture for high speed packet processing
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DOI：
10.1049/iet-cdt:20060085
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发表时间：
2005-08
期刊：
影响因子：
--
通讯作者：
Z. Liu;K. Zheng;B. Liu
中科院分区：
文献类型：
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作者：
Z. Liu;K. Zheng;B. Liu
许多网络处理器（NPs）中使用的公开内存层次结构非常昂贵，而且难以有效利用。另一方面，由于传统缓存在网络应用的局部利用效率较低，也不能直接集成到NP中。本文提出了一种新的内存层次结构构件——分割控制缓存。该方案采用两个独立的低延迟存储器来临时保存基于流和应用相关的信息，利用这两种类型的数据所表现出的不同局部性行为。数据移动由专门设计的硬件操作，从而使程序员从内存管理的细节中解脱出来。性能评估表明，在OC-3c的链路速率下，该组件在路由查找中仅使用16 KB内存即可实现90%以上的命中率，并为大多数网络应用的实现提供了足够的灵活性。
The exposed memory hierarchies employed in many network processors (NPs) are expensive and hard to be effectively utilized. On the other hand, conventional cache cannot be directly incorporated into NP either because of its low efficiency in locality exploitation for network applications. In this paper, a novel memory hierarchy component, called split control cache, is presented. The proposed scheme employs two independent low latency memory stores to temporarily hold the flow-based and application-relevant information, exploiting the different locality behaviors exhibited by these two types of data. Data movement is manipulated by specially designed hardware to relieve the programmers from details of memory management. Performance evaluation shows that this component can achieve a hit rate of over 90% with only 16 KB of memories in route lookup under link rate of OC-3c and provide enough flexibility for the implementation of most network applications.