A 3.9ppm/degrees C 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference
A 3.9ppm/degrees C 8.8nW and High PSRR Subthreshold CMOS Multiple Voltage Reference
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3.9ppm/摄氏度 8.8nW 和高 PSRR 亚阈值 CMOS 多电压基准
DOI：
10.1049/cje.2016.11.005
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发表时间：
2017
影响因子：
1.2
通讯作者：
Yang Zhi
中科院分区：
文献类型：
--
作者：
Jiang Mei;Li Yongquan;Yang Zhi
提出了一种具有低温度系数（TC）和三输出的、兼容高电源抑制比（PSRR）和低功耗的基准电压。所提出的基准电路在所有晶体管偏置于亚阈值区域时工作，提供340mV、680mV和1020mV三个参考电压。亚阈值MOSFET设计允许电路在1.2V电源电压下以7.4nA的最小电流消耗工作。在1.2至3V的电源电压范围内，平均线路灵敏度为1.7%/V。在100Hz和10MHz下，340mV输出电压的电源抑制比（PSRR）分别大于51.9dB和120.4dB。蒙特卡罗模拟显示，平均TC为3.9ppm/◦C，标准偏差为1ppm/◦C，一组500个样品，温度范围为-30◦C至100◦C。给出的电压基准的有效区域为0.003mm2。
A voltage reference with low Temperature coefficient (TC) and three outputs, which is compatible with high Power supply rejection ratio (PSRR) and low power consumption, is presented in this paper. The proposed reference circuit operating with all transistors biased in subthreshold region, provides three reference voltages of 340mV, 680mV, and 1020mV. Subthreshold MOSFET design allows the circuit to work with minimum current consumption of 7.4nA at the supply voltage 1.2V. The mean line sensitivity is 1.7%/V under a supply voltages ranging from 1.2 to 3V. The Power supply rejection ratio (PSRR) of 340mV output voltage simulated at 100Hz and 10MHz is over than 51.9dB and 120.4dB, respectively. Monte Carlo simulation shows a mean TC is 3.9ppm/◦C with a standard deviation of 1ppm/◦C over a set of 500 samples, in a temperature range from –30◦C to 100◦C. The active area of the presented voltage reference is 0.003mm2.