A Hardware-Oriented Echo State Network and its FPGA Implementation
A Hardware-Oriented Echo State Network and its FPGA Implementation
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DOI：
10.2991/jrnal.k.200512.012
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发表时间：
2020-06-01
影响因子：
0.3
通讯作者：
Tamukoh, Hakaru
中科院分区：
文献类型：
--
作者：
Honda, Kentaro;Tamukoh, Hakaru
本文提出了一种回声状态网络（ESN）的现场可编程门阵列（FPGA）的实现。该方法通过使用定点运算、权值量化、累加运算和高效的并行模块来减少硬件资源。通过实验验证了所设计电路的性能，包括正弦和余弦波的预测。实验结果表明，该电路支持200 MHz的工作频率，有利于更快地计算ESN算法相比，中央处理器。(c)2020作者出版社：Atlantis Press SARL这是一篇开放获取的文章，在CC BY-NC 4.0许可证下分发（http：//creativecommons.org/licenses/by-nc/4.0/）。
This paper proposes implementation of an Echo State Network (ESN) to Field Programmable Gate Array (FPGA). The proposed method is able to reduce hardware resources by using fixed-point operation, quantization of weights, which includes accumulate operations and efficient dataflow modules. The performance of the designed circuit is verified via experiments including prediction of sine and cosine waves. Experimental result shows that the proposed circuit supports to 200 MHz of operation frequency and facilitates faster computing of the ESN algorithm compared with a central processing unit. (c) 2020 The Authors. Published by Atlantis Press SARL. This is an open access article distributed under the CC BY-NC 4.0 license (http://creativecommons.org/licenses/by-nc/4.0/).