A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array
A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array
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具有时间交错相位检测器阵列的 622 Mb/s CMOS 时钟恢复 PLL
DOI：
10.1109/isscc.1996.488569
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发表时间：
1996
期刊：
影响因子：
--
通讯作者：
W. Song
中科院分区：
文献类型：
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作者：
Inyeol Lee;C. Yoo;Wonchan Kim;S. Chai;W. Song
采用0.8 μ/mCMOS工艺实现了一个用于SDH/SONET OC-12的622 Mb/s时钟恢复锁相环。该锁相环采用时间交织鉴相技术，同时完成时钟恢复和1：8解复用。该器件采用5 V单电源供电，功耗为200 mW，内核占用800/spl times/900 /spl mu/m/sup 2/。恢复的78 MHz时钟的RMS抖动为46 ps（0.36%）。
A 622 Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8 /spl mu/m CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200 mW with a single 5 V supply, whose core occupies 800/spl times/900 /spl mu/m/sup 2/. RMS jitter of the recovered 78 MHz clock is 46 ps (0.36%).