Testing of core-based systems-on-a-chip
Testing of core-based systems-on-a-chip
复制标题
基于内核的片上系统的测试
DOI：
10.1109/43.913760
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
N. Jha
中科院分区：
文献类型：
--
作者：
S. Ravi;G. Lakshminarayana;N. Jha
用于测试基于核的片上系统（SOC）的可用技术不提供用于综合低开销测试架构和紧凑测试解决方案的系统手段。在本文中，我们提供了一个全面的框架，产生低开销的紧凑型测试解决方案的SOC。首先，我们为解决核心测试需求、核心访问和测试硬件添加等问题建立了一个共同基础。为此，我们引入有限状态自动机（FSA）的建模测试，透明模式，并测试硬件的行为。在许多情况下，测试会针对不同的测试数据重复一组基本的测试操作，这些测试数据可以再次使用FSA进行建模。虽然早期的工作可以推导出一个单一的符号测试的寄存器传输级（RTL）电路作为一个有限状态自动机的模块，这项工作扩展的方法，系统级，另外有助于满足性为基础的解决方案的问题，应用一系列的测试分阶段的时间。这个问题是已知的可测性分析的瓶颈，不仅在系统级，而且在RTL。实验结果表明，使用我们的方法使SOC可测试的系统级平均面积开销仅为4.5%，同时实现了80%的平均测试应用时间比最近的方法减少。同时，它提供了100%的测试覆盖率的预先计算的测试集/序列的嵌入式核心。
Available techniques for testing of core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesizing low-overhead test architectures and compact test solutions. In this paper, we provide a comprehensive framework that generates low-overhead compact test solutions for SOCs. First, we develop a common ground for addressing issues such as core test requirements, core access, and testing hardware additions. For this purpose, we introduce finite-state automata (FSA) for modeling tests, transparency modes, and testing hardware behavior. In many cases, the tests repeat a basic set of test actions for different test data that can again be modeled using FSA. While earlier work can derive a single symbolic test for a module in a register-transfer level (RTL) circuit as a finite-state automaton, this work extends the methodology to the system level and additionally contributes a satisfiability-based solution to the problem of applying a sequence of tests phased in time. This problem is known to be a bottleneck in testability analysis not only at the system level, but also at the RTL. Experimental results show that the system-level average area overhead for making SOCs testable with our method is only 4.5%, while achieving an average test application time reduction of 80% over recent approaches. At the same time, it provides 100% test coverage of the precomputed test sets/sequences of the embedded cores.