Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM
Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM
复制标题
3-D 集成工艺对高可靠 3-D DRAM 薄型 DRAM 芯片内存保持特性的影响
DOI：
10.1109/ted.2013.2295244
复制
发表时间：
2014
影响因子：
3.1
通讯作者：
M. Koyanagi
中科院分区：
文献类型：
--
作者：
Kang;S. Tanikawa;M. Murugesan;H. Naganuma;J. Bea;T. Fukushima;Tetsu Tanaka;M. Koyanagi
评估了三维集成工艺对薄化DRAM芯片存储器保持特性的影响。采用底面填充方式与中介层正面向下键合的DRAM芯片，其存储单元的保持特性随芯片厚度的减小而降低，特别是在40 μm以下时，保持特性急剧下降。同时，在没有底部填充的情况下键合的DRAM芯片中，DRAM单元的保持特性在30 μm厚度之前相对不那么退化，但在20 μm厚度以下突然退化。CMP处理的薄化DRAM芯片中的DRAM单元的保持特性在300 °C退火下从背侧表面故意扩散Cu之后显著地降低，而与阱结构无关。同时，在经DP处理的薄化DRAM芯片中的DRAM单元的保持特性即使在300 °C退火的Cu扩散之后也没有劣化。
The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40- μm thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30- μm thickness, but suddenly degraded below 20- μm thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 °C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 °C annealing.