Direct synthesis of submillimeter-sized few-layer WS2 and WS0.3Se1.7 by mist chemical vapor deposition and its application to complementary MOS inverter
Direct synthesis of submillimeter-sized few-layer WS2 and WS0.3Se1.7 by mist chemical vapor deposition and its application to complementary MOS inverter
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DOI：
10.1088/1361-6641/ac84fb
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发表时间：
2022-07
影响因子：
1.9
通讯作者：
A. Kuddus;K. Yokoyama;H. Shirai
中科院分区：
文献类型：
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作者：
A. Kuddus;K. Yokoyama;H. Shirai
研究了用雾化学气相沉积(CVD)法直接合成亚毫米尺寸的少层二硫化钨(WS2)和硫化钨(WS0.3Se1.7)作为金属氧化物半导体场效应晶体管(MOSFET)的沟道层。用(NH_4)_2WS_4溶解于N-甲基-2-吡咯烷酮，在封闭的石英管中间歇雾化，在热生长的−和薄雾CVD生长的高κ非晶氧化铝衬底上沉积了WS_2和WS_2-Se_x原子单层/双层薄膜。此外，炉膛温度、每周期前体雾的供应/储存次数和前体浓度被认为是变量。因此，通过调整沉积条件，在高μa-Al0.74Ti0.26O介质层上获得了晶粒尺寸为700~800κm的WS2和WS0.3Se1.7。随后，将这几层WS2和WS0.3Se1.7分别用作MOSFET的沟道层，分别采用金电极和铂源漏电极进行了n沟道和p沟道行为。在n-WS2和p-WS0.3Se1.7沟道场效应管中，获得了∼52和∼41cm2 V−1 S−1的平均迁移率，阈值电压为−0.2(0.3)V，开关比分别为∼1×10 6和∼6×10 5。此外，利用该n沟道和p沟道FET设计了电隔离互补逆变器电路，获得了4~5的增益。这项研究的结果表明，雾CVD可以作为FET中应用的沟道绝缘层和栅绝缘层的一致制造技术。
This study investigated the direct synthesis of submillimeter-sized few-layer tungsten disulfide (WS2) and tungsten sulfoselenide (WS0.3Se1.7) using the mist chemical vapor deposition (CVD) method as a channel layer for metal-oxide-semiconductor field-effect transistors (MOSFETs). The atomic mono/bilayers WS2 and WS2−x Se x were deposited on thermally grown SiO2 and mist-CVD-grown high-κ amorphous aluminum titanium oxide coated on p+-Si substrates by an intermittent mist supply in a closed quartz tube from (NH4)2WS4 dissolved in N-methyl-2-pyrrolidone. Further, the furnace temperatures, supply/storage times of the precursor mist per cycle, and precursor concentration were considered variables. Consequently, few-layer WS2 and WS0.3Se1.7 with grain sizes of 700–800 μm were obtained on the high-κ a-Al0.74Ti0.26O y dielectric layers through adjustments to the deposition conditions. Subsequently, this few-layer WS2 and WS0.3Se1.7 were applied as channel layers in MOSFETs, which showed n- and p-channel behaviors using gold and platinum source/drain electrodes, respectively. Further, average mobilities of ∼52 and ∼41 cm2 V−1 s−1 were obtained with a threshold voltage of −0.2 (0.3) V and on-off ratios of ∼1 × 106 and ∼6 × 105 in n-WS2 and p-WS0.3Se1.7 channel FETs, respectively. Moreover, this n- and p-channel FETs were used to design an electrically isolated complementary inverter circuit, and a gain of 4–5 was obtained. The findings of this study suggest that mist CVD can be a consistent manufacturing technique for both the channel and gate insulating layers applied in FETs.