NUPLet: A Photonic Based Multi-Chip NUCA Architecture
NUPLet: A Photonic Based Multi-Chip NUCA Architecture
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NUPLet：基于光子的多芯片 NUCA 架构
DOI：
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发表时间：
2017
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通讯作者：
S. Sarangi
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作者：
Janibul Bashir;S. Sarangi
面积、制造良率和缺乏可扩展的互连将单芯片设计限制在少量的核（16-32）上。然而，在硅光子学的帮助下的多芯片设计可以克服面积和产量的限制，并使设计虚拟芯片成为可能，该虚拟芯片可以扩展到大量的内核。遗憾的是，这种设计的可扩展性受到芯片间消息的高存储量和远程缓存组中相对较低的命中率的限制。在本文中，我们提出了NUPlet，一个多芯片架构，试图通过分离芯片内和芯片间网络来消除这些限制。提出了在虚拟芯片上采用非均匀缓存结构（NUCA）的方案，以减少片间通信，提高末级缓存的命中率。此外，我们提出了一种预测机制，用于预测网络中的芯片间消息的数量。这用于相应地调制激光器，并降低静态功耗。我们模拟了一个基于四芯片的NUPlet设计，每个芯片包含32个内核。对于一套Splash 2和Parsec基准测试，与其他最先进的提案相比，NUPlet将末级缓存命中率提高了70%。此外，NUPlet将性能提高了28%，功耗降低了39%，ED^2降低了41%。
Area, manufacturing yield and lack of scalable interconnects restrict single chip designs to a small number of cores (16-32). However, multi-chip designs with the help of silicon photonics can overcome area and yield constraints and make it possible to design a virtual chip, which can scale to a large number of cores. Sadly, the scalability of such designs is limited bythehighpercentageofinter-chipmessagesandrelativelylower hit rate in remote cache banks. In this paper, we propose NUPLet, a multi-chip architecture that tries to remove these limitations by separating the intra and inter chip networks. It proposes to use a non-uniform cache architecture (NUCA) scheme on top of a virtual chip in order to decreaseinterchipcommunicationandincreasethehitrateinthe last level cache. In addition, we propose a prediction mechanism for predicting the number of inter chip messages in the network. This is used to modulate the laser accordingly, and reduce static power consumption. We simulated a four chip based NUPLet design with each chip containing 32 cores. For a suite of Splash2 and Parsec benchmarks, NUPLet increased the last level cache hit rate by 70% as compared to other state of the art proposals. Furthermore, NUPLet improved performance by 28%, reduced power consumption by 39%, and reduced ED^2 by 41%.