On testing timing-speculative circuits
On testing timing-speculative circuits
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DOI：
10.1145/2463209.2488771
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发表时间：
2013-05
期刊：
影响因子：
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通讯作者：
F. Yuan;Yannan Liu;W. Jone;Q. Xu
中科院分区：
文献类型：
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作者：
F. Yuan;Yannan Liu;W. Jone;Q. Xu
电路级时序推测允许不常见的时序错误发生并在线纠正，是最有前途的容变设计技术之一。然而，如何有效地测试时序推测电路，还没有在文献中提到。这是一个具有挑战性的问题，因为传统的扫描技术不能为这样的电路提供足够的可控性和可观察性。在本文中，我们提出了新的技术，以实现高故障覆盖率的时序推测电路，而不会产生高的可测性设计成本。在多个基准电路上的实验结果证明了该方法的有效性。
By allowing the occurrence of infrequent timing errors and correcting them online, circuit-level timing speculation is one of the most promising variation-tolerant design techniques. How to effectively test timing-speculative circuits, however, has not been addressed in the literature. This is a challenging problem because conventional scan techniques cannot provide sufficient controllability and observability for such circuits. In this paper, we propose novel techniques to achieve high fault coverage for timing-speculative circuits without incurring high design-for-testability cost. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed solution.