Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process
Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process
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DOI：
10.23919/ispsd.2017.7988958
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发表时间：
2017-05
期刊：
影响因子：
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通讯作者：
C. Schmidt;G. Spitzlsperger
中科院分区：
文献类型：
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作者：
C. Schmidt;G. Spitzlsperger
提出了BCD技术的一个新概念，它包括在减薄的背面上处理晶片，并且提供-类似于SOI技术-功率器件的完全电介质隔离。在传统BCD技术中遇到的p-LDMOS的击穿电压的限制通过用形成在晶片背面上的n+区域代替通常应用的深n阱层并且通过用TSV将n+区域连接到正面上的源极电势来克服。所制备的漂移长度为5.7μm的p-LDMOS的击穿电压（BVdss）为−115 V，导通电阻（罗恩）为320 mΩ mm。TCAD模拟发现，在STI下方添加n型RESURF层可以进一步优化p-LDMOS的BVdss、罗恩和电SOA。
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.