On the reuse of timing resilient architecture for testing path delay faults in critical paths
On the reuse of timing resilient architecture for testing path delay faults in critical paths
复制标题
关于重用时序弹性架构来测试关键路径中的路径延迟故障
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Alexandre M. Amory
中科院分区：
文献类型：
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作者：
F. Kuentzer;L. Juracy;Alexandre M. Amory
能效已成为当代应用最常见和最重要的要求之一，这增加了对工作在阈值电压电平附近的芯片的需求，这不幸地恶化了工艺、电压和温度(PVT)变化的影响。应对PVT变化的另一种解决方案是时序弹性体系结构，例如同步剃刀系列和异步刀片模板，它们依赖错误检测逻辑(EDL)来检测时序冲突并从中恢复。一方面，时序弹性体系结构的使用使路径延迟测试更具挑战性，因为它不是简单的通过或失败测试的问题。另一方面，我们展示了时序弹性架构，例如刀片，为设计关键路径的低成本在线延迟测试提供了机会。在32位MIPS处理器和加密核上进行了功能测试，结果显示了面积开销和故障覆盖率。
Energy efficiency has become one of the most common and important demands for contemporary applications, increasing the desire for chips that operate near the threshold voltage levels, which unfortunately worsens the effects of process, voltage, and temperature (PVT) variability. An alternative solution to cope with PVT variations are the timing resilient architectures, such as the synchronous Razor family and the asynchronous Blade template, that rely on error detection logic (EDL) to detect and recover from timing violations. On one hand, the use of timing resilient architectures makes the path delay testing more challenging because it is not a matter of simple pass or fails the test. On the other hand, we show that timing resilient architectures, such as Blade, present opportunities to design low-cost online delay testing of the critical paths. Results show the area overhead and fault coverage using functional testing on a 32-bit MIPS CPU and a crypto core.