1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-$\mu\hbox{m}$ CMOS Technology
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-$\mu\hbox{m}$ CMOS Technology
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采用 0.18-$muhbox{m}$ CMOS 技术的 1.25/2.5-Gb/s 双比特率突发模式时钟恢复电路
DOI：
10.1109/tcsii.2006.884120
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
W. Choi
中科院分区：
文献类型：
--
作者：
P. Han;W. Choi
提出了一种新颖的双比特率结构的突发模式时钟恢复电路。它利用两个门控振荡器将时钟与数据边沿对齐，并可以在半速率时钟模式下工作，使数据吞吐量加倍，也可以在全速率时钟模式下工作。门控振荡器复位相位控制方案使门控振荡器的起始相位根据当前时钟相位在0度和180度之间重复交替。采用0.18 μ mCMOS工艺设计了一个原型芯片，并通过测试验证了其1.25/2.5-Gb/s双模工作
A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and 180deg according to the current clock phase. A prototype chip was designed with the 0.18-mum CMOS technology, and a 1.25/2.5-Gb/s dual-mode operation was verified by measurement