Analysis of within-die process variation in 65nm FPGAs
Analysis of within-die process variation in 65nm FPGAs
复制标题
65nm FPGA 芯片内工艺变化分析
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
S. Trimberger
中科院分区：
文献类型：
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作者：
Tim Tuan;A. Lesea;C. Kingsley;S. Trimberger
FPGA是研究芯片内工艺变化的一个很好的平台，因为测试结构可以使用可重构逻辑在产品硅中实现。这种方法可以实现非常高的覆盖率，而不会浪费其他有用的硅面积。在本文中，我们提出了一个65纳米FPGA的芯片内延迟变化的详细分析。我们使用密集分布的测试振荡器来测量在一个大样本的模具内的性能变化，并通过后处理识别随机和空间相关的系统组件。最后，我们评估了静态时序分析中模内系统变化的好处。
FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die performance variation across a large sample of dies, and identify both random and spatially correlated systematic components through post-processing. Finally, we evaluate the benefit of modeling within-die systematic variation in static timing analysis.