Optimising dislocation-engineered silicon light-emitting diodes
Optimising dislocation-engineered silicon light-emitting diodes
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优化位错工程硅发光二极管
DOI：
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发表时间：
2006
期刊：
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通讯作者：
K. Homewood
中科院分区：
文献类型：
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作者：
M. Milosavljević;M. Lourenço;G. Shao;R. Gwilliam;K. Homewood
本文介绍了优化位错工程硅发光二极管（DELEDs）电致发光（EL）效率的可能性。在离子能量为30 keV和1×1015 ions/cm2的恒定条件下，在n型（100）Si晶片中注入硼制备了二极管。在30 ~ 60 min的快速热处理过程中，不同的退火时间改变了位错环的密度和覆盖面积。结果表明，电振效率与环路的数量和覆盖面积直接相关。在1-5分钟的退火过程中，获得了最高的环路数量，约5×109 /cm2，面积覆盖率约为50%。这种环路分布导致了最佳的去电二极管，随着工作温度（80-300 K）的增加，它具有最高的EL响应和最大的EL强度增加。这项工作的结果证实了先前引入的由位错环边缘引起的局部应力引起的电荷-载流子空间限制模型，该模型阻止载流子扩散到非辐射复合中心，并增强了硅带边缘的辐射跃迁。
This article presents a study of the possibilities of optimising the electroluminescence (EL) efficiency of dislocation-engineered silicon light-emitting diodes (DELEDs). The diodes were produced by implantation of boron in n-type (100)Si wafers, at a constant ion energy and fluence, of 30 keV and 1×1015 ions/cm2, respectively. The density and the areal coverage by dislocation loops were varied by applying different annealing times in a rapid thermal processing, from 30 s to 60 min. It is shown that the EL efficiency is directly correlated to the number and areal coverage by the loops. The highest population of loops, ∼5×109 /cm2, and an areal coverage of around 50% were achieved for 1–5 min annealing. This loop distribution results in optimal DELEDs, having the highest EL response and the largest increase of EL intensity with operating temperature (80–300 K). The results of this work confirm a previously introduced model of charge-carrier spatial confinement by a local stress induced by the edge of the dislocation loops, preventing carrier diffusion to non-radiative recombination centres and enhancing radiative transitions at the silicon band edge.