Efficient and secure intellectual property (IP) design with split fabrication
Efficient and secure intellectual property (IP) design with split fabrication
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DOI：
10.1109/hst.2014.6855561
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发表时间：
2014-05
期刊：
影响因子：
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通讯作者：
Kaushik Vaidyanathan;Renzhi Liu;Huseyin Ekin Sumbul;Qiuling Zhu;F. Franchetti;Larry Pileggi
中科院分区：
文献类型：
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作者：
Kaushik Vaidyanathan;Renzhi Liu;Huseyin Ekin Sumbul;Qiuling Zhu;F. Franchetti;Larry Pileggi
拆分制造是将IC拆分成不可信和可信的层的过程，有助于访问世界上可用的最先进的半导体制造能力，而无需披露设计意图。虽然研究人员已经在分裂制造的背景下研究了逻辑块的安全性，但作为SoC的另一个关键组件的IP块的安全性还没有被检查。我们对IP块设计，特别是嵌入式存储器和模拟元件的安全分析表明，由于使用了标准化的布局和叶单元布局，它们在不可信的代工厂容易受到“识别攻击”。我们提出了高效和安全地设计这些模块的方法，并使用130 nm拆分制造的测试芯片来验证其有效性。
Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While researchers have investigated the security of logic blocks in the context of split fabrication, the security of IP blocks, another key component of an SoC, has not been examined. Our security analysis of IP block designs, specifically embedded memory and analog components, shows that they are vulnerable to “recognition attacks” at the untrusted foundry due to the use of standardized floorplans and leaf cell layouts. We propose methodologies to design these blocks efficiently and securely, and demonstrate their effectiveness using 130nm split fabricated testchips.