High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates
High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates
复制标题
采用多晶 SiGe 栅极的高性能深亚微米 CMOS 技术
DOI：
10.1109/16.831003
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发表时间：
2000
影响因子：
3.1
通讯作者：
P. Woerlee
中科院分区：
文献类型：
--
作者：
Y. Ponomarev;P. Stolk;C. Salm;J. Schmitz;P. Woerlee
研究了多晶SiGe作为深亚微米CMOS栅材料的应用。当用SiGe(对于小于0.5的Ge组分)取代多晶硅形成晶体管的栅电极时，证明了与标准的CMOS工艺完全兼容。PMOS晶体管的性能改善是通过仔细优化晶体管沟道轮廓和p型栅功函数来实现的，后者通过改变栅中Ge摩尔分数来实现。对于0.18/SPL mU/m的CMOS代，我们记录到电流驱动增加了20%，通道跨导增加了10%，亚阈值摆幅从82 mV/dec提高到75 mV/dec，从而实现了出色的“开”/“关”电流比。同时，NMOS晶体管的性能不受栅极材料替代的影响。
The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 /spl mu/m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent "on"/"off" currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitution.