The Entangling Instruction Prefetcher
The Entangling Instruction Prefetcher
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纠缠指令预取器
DOI：
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发表时间：
2020
影响因子：
2.3
通讯作者：
A. Jimborean
中科院分区：
文献类型：
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作者：
Alberto Ros;A. Jimborean
指令预取是设计高性能计算机的一项基本技术。在设计一个高效的预取器时，有三个关键属性需要考虑：及时性、覆盖率和准确性。时间性是一个基本属性，因为过早地引入指令会增加指令在使用之前从该高速缓存中被逐出的风险，而过晚地请求指令会导致指令到达时超过其指定的执行时间。覆盖率对于减少指令缓存未命中的数量（有足够的预取）和准确性非常重要，以确保预取器不会污染该高速缓存或与其他硬件机制产生负面影响（没有太多的预取）。这封信介绍了纠缠指令预取器，纠缠指令提供及时性。预取器的工作原理是找到哪个指令应该触发后续指令的预取，并考虑每个缓存未命中的延迟。预取器经过仔细调整，以兼顾覆盖率和准确性。我们的评估表明，纠缠I预取器平均提高了29.3%的性能，覆盖率为94.9%，准确率为77.4%。
Prefetching instructions is a fundamental technique for designing high-performance computers. There are three key properties to consider when designing an efficient and effective prefetcher: timeliness, coverage, and accuracy. Timeliness is an essential property, as bringing instructions too early increases the risk of the instructions being evicted from the cache before their use while requesting them too late can lead to the instructions arriving past their designated execution time. Coverage is important to reduce the number of instruction cache misses (there is enough prefetching), and accuracy to ensure that the prefetcher does not pollute the cache or interacts negatively with the other hardware mechanisms (there is not too much prefetching). This letter presents the Entangling instruction prefetcher that entangles instructions to provide timeliness. The prefetcher works by finding which instruction should trigger the prefetch for a subsequent instruction, accounting for the latency of each cache miss. The prefetcher is carefully adjusted to account for both coverage and accuracy. Our evaluation shows that the Entangling I-prefetcher increases performance by 29.3 percent on average, with a coverage of 94.9 percent and accuracy of 77.4 percent.