Author ' s personal copy A versatile linear insertion sorter based on an FIFO scheme
Author ' s personal copy A versatile linear insertion sorter based on an FIFO scheme
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发表时间：
2009
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通讯作者：
Roberto Perez-Andrade;R. Cumplido;C. Feregrino-Uribe;Fernando Martin del Campo
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作者：
Roberto Perez-Andrade;R. Cumplido;C. Feregrino-Uribe;Fernando Martin del Campo
提出了一种基于先进先出(FIFO)的线性排序器。它能够丢弃最旧的存储数据并插入输入数据，同时保持存储数据的其余部分在单个时钟周期内排序。这种类型的分类器可以用作协处理器或专用体系结构中的模块，这些专用体系结构不断需要基于顺序统计量处理非线性滤波器的数据。这种FIFO排序过程由四个不同的并行函数描述，它们利用了自然的硬件并行性。该体系结构由相同的处理元素组成，因此可以根据特定的应用需求很容易地适应任何数据长度。紧凑的相同处理元件的使用导致了高性能而又小巧的架构。为了理解所提出的分类器的功能和初始化，文中给出了一些例子。给出了以现场可编程门阵列(FPGA)为目标的该结构的综合结果，并与其他已报道的基于硬件的分类器进行了比较。文中还给出了几种不同位宽的排序元素的可扩展性结果。&2009爱思唯尔有限公司版权所有。
A linear sorter based on a first-in first-out (FIFO) scheme is presented. It is capable of discarding the oldest stored datum and inserting the incoming datum while keeping the rest of the stored data sorted in a single clock cycle. This type of sorter can be used as a co-processor or as a module in specialized architectures that continuously require to process data for non-linear filters based on order statistics. This FIFO sorting process is described by four different parallel functions that exploit the natural hardware parallelism. The architecture is composed of identical processing elements; thus it can be easily adapted to any data lengths, according to the specific application needs. The use of compact identical processing elements results in a high performance yet small architecture. Some examples are presented in order to understand the functionality and initialization of the proposed sorter. The results of synthesizing the proposed architecture targeting a field programmable gate array (FPGA) are presented and compared against other reported hardware-based sorters. The scalability results for several sorted elements with different bits widths are also presented. & 2009 Elsevier Ltd. All rights reserved.