Identifying and predicting timing-critical instructions to boost timing speculation
Identifying and predicting timing-critical instructions to boost timing speculation
复制标题
识别和预测时序关键指令以促进时序推测
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
R. Joseph
中科院分区：
文献类型：
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作者：
Jing Xin;R. Joseph
已经提出了电路级的时机猜测，以减少对设计边缘的依赖并消除功率/性能开销的技术。最近的工作提出了微构造方法，以动态检测和从处理器逻辑中的定时错误中恢复。现有工作在很大程度上取决于统计错误模型，并且没有在静态指令级别评估错误率的潜在差异。在本文中，我们为执行管道分析了门级硬件模型，并在指令级别的错误率和数据依赖性引起的指令级错误率中表现出明显的位置。我们建议在指令级别和错误填充技术上动态预测定时错误，以避免定时错误的全部恢复成本。我们表明，通过简单的预测策略，我们的机制可以平均降低错误恢复所产生的绩效罚款的80％。这使我们可以通过使用相同的动态自适应调音机制来减轻定时猜测的某些局限性，并将能源效率提高21％。
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gate-level hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.