A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies
A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies
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DOI：
10.1109/tvlsi.2009.2016205
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发表时间：
2010-05
影响因子：
2.8
通讯作者：
H. Yamauchi
中科院分区：
文献类型：
--
作者：
H. Yamauchi
本文比较了多种SRAM容限辅助解决方案的面积扩展能力，这些解决方案不仅基于从6T到8T和10T的单元拓扑变化的各种努力，而且包括用于单元端子偏置的多个电压源和读写的时序控制。根据不断增加的VT随机变化(？VT)和导致SRAM缩放速度减慢对每个设计解决方案所需的面积开销的影响来分析各种SRAM解决方案。为了预测不同SRAM解决方案之间的面积缩放趋势，假设了悲观和乐观两种不同的VT增加情景，其中o-Vt分别变为>；130 mV和抑制到85 mV和75 mV。
This paper compares area scaling capabilities of many kinds of SRAM margin-assist solutions for VT variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporation of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever-increasing VT random variation (¿VT)> resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different ¿VT-increasing scenarios of being pessimistic and optimistic are assumed, where o-vt becomes > 130 mV and suppressed to 85 and 75 mV, respectively.