Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms
Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms
复制标题
决策树集成的可扩展推理：CPU-FPGA 平台的灵活设计
DOI：
10.23919/fpl.2017.8056784
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
G. Alonso
中科院分区：
文献类型：
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作者：
Muhsen Owaida;Hantian Zhang;Ce Zhang;G. Alonso
决策树集成算法被广泛应用，成为基于决策树分类器的事实上的算法。在树推理过程中，集成中的不同树可以并行处理，使其成为FPGA的合适用例。然而，大型树集合需要仔细地将树映射到片上存储器和存储器访问管理。因此，现有的FPGA解决方案无法扩展到数十棵树之外，并且缺乏支持不同树集合的灵活性。在本文中，我们提出了一个FPGA树集成分类器连同一个软件驱动程序，以有效地管理FPGA的内存资源。分类器架构有效利用FPGA的资源，在片内存储器中容纳50万个树节点，在FPGA上完全处理树集合时，与10线程CPU实现相比，可提供高达20倍的加速比。它还可以将CPU和FPGA联合收割机扩展到无法装入片内存储器的树集合，与纯CPU实现相比，实现了高达一个数量级的加速。此外，分类器架构可以在运行时编程以处理不同的树集成大小。
Decision tree ensembles are commonly used in a wide range of applications and becoming the de facto algorithm for decision tree based classifiers. Different trees in an ensemble can be processed in parallel during tree inference, making them a suitable use case for FPGAs. Large tree ensembles, however, require careful mapping of trees to on-chip memory and management of memory accesses. As a result, existing FPGA solutions suffer from the inability to scale beyond tens of trees and lack the flexibility to support different tree ensembles. In this paper we present an FPGA tree ensemble classifier together with a software driver to efficiently manage the FPGA's memory resources. The classifier architecture efficiently utilizes the FPGA's resources to fit half a million tree nodes in on-chip memory, delivering up to 20× speedup over a 10-threaded CPU implementation when fully processing the tree ensemble on the FPGA. It can also combine the CPU and FPGA to scale to tree ensembles that do not fit in on-chip memory, achieving up to an order of magnitude speedup compared to a pure CPU implementation. In addition, the classifier architecture can be programmed at runtime to process varying tree ensemble sizes.