Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications
Gate Leakage in Non-Volatile Ferroelectric Transistors: Device-Circuit Implications
复制标题
非易失性铁电晶体管中的栅极漏电流：器件电路影响
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
S. Gupta
中科院分区：
文献类型：
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作者：
S. Thirumala;S. Gupta
铁电场效应管（fefet）为设计陡峭开关和非易失性（NV）晶体管提供了有趣的可能性。fefet可以通过以下两种方式实现：(i)在铁电（FE，例如HZO）和介电（DE）之间有一个内部金属层（w- iml）或（ii）在DE上直接集成FE而不使用内部金属（w/o-IML）。每个设备都有自己的问题[2][3]。w/o-IML的FET可能受到HZO缺陷（导致捕获/去捕获[2]）和不均匀的FE电场（由于底层FET）的影响，这可能导致性能下降/可变性[4]。另一方面，在fefet w-IML中，IML是浮动的，栅极泄漏（GL）可能导致几个问题。在[3]中讨论了GL对fet陡开关的影响。同样，有必要了解在NV场效应管中GL的影响。在本文中，我们分析了栅极泄漏在NV fet w-IML中的影响，并描述了两种NV状态之间的可分性如何由于GL而丢失。我们提出了栅极工作函数（GWF）工程以及基于ffet存储器的修改读取方案，以抵消GL的影响。
Ferroelectric FETs (FEFETs) offer intriguing possibilities for the design of steep switching and non-volatile (NV) transistors [1]. FEFETs may be realized either: (i) with an internal metal layer (w-IML) between ferroelectric (FE e.g. HZO) and dielectric (DE) or (ii) direct integration of FE on DE without the use of internal metal (w/o-IML). Each of these devices have their own issues [2], [3]. FEFETs w/o-IML may be affected by defects in HZO (resulting in trapping/de-trapping [2]), and non-uniform FE electric fields (due to the underlying FET), which may lead to performance degradation/variability [4]. On the other hand, in FEFETs w-IML, the IML is floating and the gate leakage (GL) can result in several issues. The effect of GL in the context of steep switching of FEFETs has been discussed in [3]. Similarly, there is a need to understand the impact of GL in NV FEFETs. In this paper, we analyze the implications of gate leakage in NV FEFETs w-IML and describe how distinguishability between the two NV states can be lost due to GL. We propose gate workfunction (GWF) engineering along with a modified read scheme for FEFET based memory to counter the effect of GL.