HMLib: Efficient Data Transfer for HLS Using Host Memory
HMLib: Efficient Data Transfer for HLS Using Host Memory
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HMLib：使用主机内存进行 HLS 的高效数据传输
DOI：
10.1145/3543622.3573157
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发表时间：
2023
期刊：
影响因子：
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通讯作者：
Cong, Jason
中科院分区：
文献类型：
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作者：
Lo, Michael;Choi, Young-kyu;Qiao, Weikang;Chang, Mau-Chung Frank;Cong, Jason
流应用程序构成了FPGA可能加速但数据移动效率低下的工作负载的重要部分。效率低下的原因是将数据间接复制到FPGA DRAM中，而不是直接复制到其片上存储器中，从而大大降低了端到端的加速，特别是对于小型工作负载（数百个字节）。AMD Xilinx的主机存储器IP（HMI）旨在通过向开发人员提供高级综合（HLS）接口来解决数据移动问题，该接口可将数据从主机直接移动到FPGA的片上存储器。然而，与当前的编程模型相比，使用HMI纯粹用于其界面而不进行额外的代码更改会导致3.3倍的速度减慢。速度减慢主要源于OpenCL调用开销和内核控制逻辑不必要地切换状态。为了克服这些问题，我们提出了主机内存库（HMLib），一个高效的基于HLS-based库，方便代表用户的数据传输。HMLib不仅优化了运行时堆栈以实现高效的数据传输，还提供了HLS兼容和用户友好的界面。我们展示了HMLib对于流媒体应用（Deflate压缩和CRC 32）的有效性，对于小规模数据，它比OpenCL-DDR提高了36.2倍，比原始HMI提高了79.5倍，同时对于大规模输入，性能几乎没有损失。我们计划在未来开放我们的工作。
Streaming applications compose an important portion of the workloads that FPGAs may accelerate but suffer from inefficient data movement. The inefficiency stems from copying data indirectly into the FPGA DRAM rather than directly into its on-chip memory, substantially diminishing the end-to-end speedup, especially for small workloads (hundreds of kilobytes). AMD Xilinx's Host Memory IP (HMI) aims to address the data movement problem by exposing to the developer an High-Level Synthesis (HLS) interface that moves the data from the host directly to the FPGA's on-chip memory. However, using HMI purely for its interface without additional code changes incurred a 3.3x slowdown in comparison with the current programming model. The slowdown mainly originates from OpenCL call overhead and the kernel control logic unnecessarily switching states. To overcome these issues, we propose Host Memory Library (HMLib), an efficient HLS-based library that facilitates data transfer on behalf of the user. HMLib not only optimizes the runtime stack for efficient data transfer, but also provides HLS compatible and user-friendly interfaces. We demonstrate HMLib's effectiveness for streaming applications (Deflate compression and CRC32) with improvements of up to up to 36.2X over OpenCL-DDR and up to 79.5X over raw HMI for small-scale data while maintaining little-to-no performance loss for large scale inputs. We plan to open source our work in the future.