A low power and high speed PPM design for ultra wideband communications
A low power and high speed PPM design for ultra wideband communications
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用于超宽带通信的低功耗、高速 PPM 设计
DOI：
10.1109/ccece.2008.4564698
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
B. Maundy
中科院分区：
文献类型：
--
作者：
A. Yousif;M. Rashdan;J. Haslett;B. Maundy
本文介绍了一个高速脉冲位置调制器（PPM）的90 nm CMOS工艺的设计，针对红外超宽带应用。在这项工作中提出的PPM设计被证明是在500 MHz的操作具有单周期延迟，并消耗小于4 mW的直流电源。为了实现单周期延迟，在设计中实现了新颖的分层延迟线结构。为了控制工艺、温度和电源电压变化对延迟线的影响，采用PPM设计实现了延迟锁定环（DLL）。PPM与DLL电路的总功耗为7.5 mW。
This paper describes the design of a high speed Pulse Position Modulator (PPM) in the 90 nm CMOS process, targeted at ir-UWB applications. The PPM design presented in this work is shown to have single cycle latency at 500 MHz of operation and consumes less than 4 mW of DC power. In order to achieve single cycle latency, novel hierarchical delay line architecture is implemented in the design. To control process, temperature, and supply voltage variation impact on the delay line, a Delay Locked Loop (DLL) is implemented with the PPM design. The total power consumption of the PPM with the DLL circuit is 7.5 mW.