Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs
Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs
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使用表面码进行量子纠错的神经网络解码器：硬件成本性能权衡的空间探索
DOI：
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发表时间：
2022
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通讯作者：
F. Sebastiano
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文献类型：
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作者：
Ramon W. J. Overwater;M. Babaie;F. Sebastiano
量子计算机中需要量子纠错（QEC）来减轻错误对物理量子比特的影响。当采用基于表面码的QEC方案时，错误解码是经典电子后端中计算量最大的任务。解码器采用神经网络（NN）是非常适合这项任务，但其硬件实现尚未提出。这项工作提出了一个空间探索的全连接前馈神经网络解码器的小距离表面代码。我们的目标是优化神经网络的高解码性能，同时保持最低限度的硬件实现。这需要满足实时表面码解码的严格延迟约束。我们证明了基于硬件的NN解码器可以实现与其他最先进的解码算法相媲美的高解码性能，同时远低于严格的延迟<inline-formula><tex-math notation="LaTeX">要求（约440 ext{ns}）$</tex-math></inline-formula>的当前固态量子位技术的两个专用集成电路设计<inline-formula><tex-math notation="LaTeX">$（<！30 ext{ns}）$</tex-math></inline-formula>和现场可编程门阵列实现<inline-formula><tex-math notation="LaTeX">$（<！90 ext{ns}）$</tex-math></inline-formula>。这些结果表明，NN解码器是未来大规模量子计算机集成硬件实现的可行候选者。
Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements <inline-formula><tex-math notation="LaTeX">$(approx 440 ext{ns})$</tex-math></inline-formula> of current solid-state qubit technologies for both application-specific integrated circuit designs <inline-formula><tex-math notation="LaTeX">$(< !30 ext{ns})$</tex-math></inline-formula> and field-programmable gate array implementations <inline-formula><tex-math notation="LaTeX">$(<! 90 ext{ns})$</tex-math></inline-formula>. These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers.