An Improved Update Rate CDR for Interference Robust Broadband Human Body Communication Receiver
An Improved Update Rate CDR for Interference Robust Broadband Human Body Communication Receiver
复制标题
抗干扰宽带人体通信接收机更新率改进的CDR
DOI：
10.1109/tbcas.2019.2940746
复制
发表时间：
2019
影响因子：
5.1
通讯作者：
Sen, Shreyas
中科院分区：
文献类型：
--
作者：
Mehrotra, Parikha;Maity, Shovan;Sen, Shreyas
宽带人体通信(HBC)通过利用人体的导电性，实现了体域网络设备之间的能量高效通信。然而，环境干扰仍然是其实施的主要瓶颈。可以使用具有可重置积分的集成前端接收器，然后周期性采样，以实现干扰稳健的宽带HBC。然而，正如在所有宽带通信系统中所要求的，时钟数据恢复(CDR)环路是在适当时刻正确采样接收数据所必需的。与传统接收器的CDR类似，CDR需要对接收端的时钟-数据相位不匹配敏感，并采取纠正措施来减小它。除此之外，宽带HBC接收机的CDR还要求对环境干扰具有容忍性。分析了集成前端接收机传统的波特率CDR结构，提出了一种具有更高更新率的改进集成CDR结构。仿真结果表明，与传统的波特率CDR相比，提出的CDR的时钟数据频偏容限提高了2.5倍，在存在干扰的情况下，>；时钟数据频偏容限提高了1.25倍，相对于积分时钟的干扰频偏容限提高了10%。所提出的CDR还在Xilinx Spartan-3E FPGA板上实现，以实时验证其闭环功能。
Broadband Human Body Communication (HBC) enables energy efficient communication between body area network devices by utilizing the electrical conductivity property of the human body. However, environmental interference remains a primary bottleneck in its implementation. An integrating front-end receiver with resettable integration followed by periodic sampling can be utilized to enable interference robust broadband HBC. However, as required in all broadband communication systems, a Clock Data Recovery (CDR) loop is necessary to correctly sample the received data at the appropriate instant. The CDR is required to be sensitive to the clock-data phase mismatch at the receiver end and take corrective action for reducing it, similar to the CDR of a traditional receiver. In addition to that, the CDR for a broadband HBC receiver also requires to be tolerant to environmental interference. This paper analyzes the traditional Baud Rate CDR for an integrating front-end receiver and proposes a modified integrating CDR architecture with a higher update rate. Simulation results show 2.5X higher clock data frequency offset tolerance of the proposed CDR compared to the traditional Baud Rate CDR, >1.25X higher clock data frequency offset tolerance in presence of interference and >10% interference frequency offset tolerance with respect to the integration clock. The proposed CDR is also implemented in a Xilinx Spartan-3E FPGA board to validate its closed loop functionality in real time.
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