Optimizing the DRAM refresh count for merged DRAM/logic LSIs
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
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DOI：
10.1145/280756.280792
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发表时间：
1998-08
期刊：
影响因子：
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通讯作者：
T. Ohsawa;K. Kai;K. Murakami
中科院分区：
文献类型：
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作者：
T. Ohsawa;K. Kai;K. Murakami
在合并的DRAM/逻辑lsi中，由于逻辑部分产生的热量和噪声，DRAM部分的数据保留时间可能会缩短。频繁刷新会增加功耗。此外，它们干扰正常的DRAM访问，导致性能下降。为了克服这个问题，我们提出了几种DRAM刷新架构。其基本思想是消除不必要的DRAM刷新。我们估计了在几种架构模型下执行基准程序时的DRAM刷新计数。因此，在最有效的体系结构组合中，对于大多数基准测试程序，我们比传统的DRAM刷新体系结构减少了80%以上。除此之外，即使我们考虑到正常的DRAM访问，我们也在几个基准测试中获得了50%以上的降低。
In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic idea is to eliminate unnecessary DRAM refreshes. We have estimated the DRAM refresh count in executing benchmark programs under several architecture models. As a result, in the most effective combination of the architectures, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most benchmark programs. In addition to it, even when we have taken normal DRAM access into account, we have obtained more than 50% reduction for several benchmarks.