Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading

Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading
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二级缓存的争用可能会限制同时多线程的有效性

DOI：
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发表时间：
1997
期刊：
影响因子：
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通讯作者：
André Seznec
André Seznec
中科院分区：
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文献类型：
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作者：
S. Hily;André Seznec

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同时多线程（SMT）是一种通过提高处理器利用率来最大化性能的有趣方法。我们调查的问题涉及的内存层次结构与SMT的行为。首先，我们表明，忽略二级缓存竞争导致强烈高估的性能，可以预期，并可能导致不正确的结论。然后，我们探讨各种内存层次结构参数的影响。我们表明，支持的线程的数量必须设置根据该高速缓存的大小，L1缓存必须是关联的，小块必须使用。然后，对内存层次结构设计的硬件约束应该将SMT的兴趣限制在少数线程上。
Simultaneous multithreading (SMT) is an interesting way of maximizing performance by enhancing processor utilization. We investigate issues involving the behavior of the memory hierarchy with SMT. First, we show that ignoring L2 cache contention leads to strongly over-estimate the performance one can expect and may lead to incorrect conclusions. We then explore the impact of various memory hierarchy parameters. We show that the number of supported threads has to be set-up according to the cache size, that the L1 caches have to be associative and small blocks have to be used. Then, the hardware constraints put on the design of memory hierarchies should limit the interest of SMT to a few threads.