Reduction of power consumption of RSFQ circuits by inductance-load biasing
Reduction of power consumption of RSFQ circuits by inductance-load biasing
复制标题
通过电感负载偏置降低 RSFQ 电路的功耗
DOI：
10.1088/0953-2048/12/11/367
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发表时间：
1999
影响因子：
3.6
通讯作者：
Y. Kato
中科院分区：
文献类型：
--
作者：
N. Yoshikawa;Y. Kato
为了降低快速单通量量子逻辑电路的功耗，提出了一种电感负载偏置方法。其主要思想源于这样一个事实，即电流源可以由一个大电感器伴随着一个大通量。在我们的方案中，电流源由大电感Lb、小电阻Rb和小电压源Vb组成。电感负载偏置约瑟夫森传输线（JTL）的计算机模拟表明，SFQ脉冲正确传播时，Lb是足够大的，即使Rb是很小的。为了实现电感负载偏置的JTL，我们做了两种不同的布局：一种是使用一个大的偏置电感Lb的典型带状线结构的接地平面上，占用了相当大的面积;另一种使用Lb的共面带状线的形状，这花费了较小的面积。
We propose an inductance-load-biasing method in order to reduce power consumption of rapid single flux quantum (SFQ) logic circuits. The main idea arises from the fact that a current source can be made of a large inductor accompanied by a large flux. In our proposal, the current source is composed of a large inductor Lb, a small resistor Rb and a small voltage source Vb. Computer simulations of inductance-load-biased Josephson transmission lines (JTLs) show that an SFQ pulse propagates correctly when Lb is large enough even if Rb is very small. In order to implement the inductance-load-biased JTL, we have made two different layouts: one uses a large bias inductance Lb of a typical stripline structure on a ground plane which occupies a rather large area; the other uses Lb in the shape of a coplanar stripline, which costs a smaller area.