Restore truncation for performance improvement in future DRAM systems
Restore truncation for performance improvement in future DRAM systems
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DOI：
10.1109/hpca.2016.7446093
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发表时间：
2016-03
期刊：
影响因子：
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通讯作者：
Xianwei Zhang;Youtao Zhang;B. Childers;Jun Yang
中科院分区：
文献类型：
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作者：
Xianwei Zhang;Youtao Zhang;B. Childers;Jun Yang
由于位单元结构的固有限制，将DRAM缩放到20 nm以下已成为主要挑战。未来的DRAM芯片可能会受到显著变化和时序退化的影响，例如在读取和写入访问之后需要更多的时间来恢复单元数据。在本文中，我们提出了恢复截断（RT），一个低成本的恢复策略，以提高性能的DRAM模块，采用宽松的恢复时间。在访问之后，RT将位单元的电压仅恢复到将数据保持到下一个预定刷新所需的电平，而不是恢复到默认的全电压。由于缩短了恢复时间，因此在工艺变化下提高了电池的性能。我们设计了两种方案来平衡性能，能源消耗和硬件开销。我们模拟了我们提出的RT方案，并将其与现有技术进行了比较。实验结果表明，平均而言，RT提高了19.5%的性能，降低了17%的能耗。
Scaling DRAM below 20nm has become a major challenge due to intrinsic limitations in the structure of a bit cell. Future DRAM chips are likely to suffer from significant variations and degraded timings, such as taking much more time to restore cell data after read and write access. In this paper, we propose restore truncation (RT), a low-cost restore strategy to improve performance of DRAM modules that adopt relaxed restore timing. After an access, RT restores a bit cell's voltage only to the level required to persist data to the next scheduled refresh rather than to the default full voltage. Because restore time is shortened, the performance of the cell is improved under process variations. We devise two schemes to balance performance, energy consumption, and hardware overhead. We simulate our proposed RT schemes and compare them with the state of the art. Experimental results show that, on average, RT improves performance by 19.5% and reduces energy consumption by 17%.