An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots
An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots
复制标题
DOI：
10.1109/access.2020.3038161
复制
发表时间：
2020-11
期刊：
影响因子：
3.9
通讯作者：
Yuichiro Tanaka;T. Morie;H. Tamukoh
中科院分区：
文献类型：
--
作者：
Yuichiro Tanaka;T. Morie;H. Tamukoh
本研究开发了一种模拟人脑功能的智能家庭服务机器人系统，可以管理适用于任何环境的共同知识和反映其特定环境的局部知识。深度学习对于获取公共知识是有效的，因为深度学习的性能依赖于这些知识可以访问的训练量和大训练数据；然而，深度学习对于获取局部知识是无效的，因为没有大的训练数据。因此，我们提出了一个大脑启发的学习模型和系统，用于使用小训练数据获取局部知识。我们之所以关注杏仁核，是因为它的经典恐惧条件反射对于使用小训练数据的训练是有效的。我们提出了一个由多个自组织图（外侧核）和一个完全连接的神经网络（中央核）组成的杏仁核启发的经典条件反射模型，模仿杏仁核的功能和结构。将该模型应用于餐馆服务员机器人的任务中，该模型只需经过几次人机交互就能了解顾客的偏好。提出了一种面向硬件的模型算法及其数字硬件设计，并在XCZU9EG现场可编程门阵列中实现，从而加快了模型的计算速度，降低了模型的功耗。面向硬件的算法减少了需要大量硬件资源的乘法运算和指数函数。150 MHz下的硬件性能比Arm Cortex-A53上的软件实现速度快1273倍，芯片功耗为5.009 W。
This study develops an intelligent system for home service robots mimicking human brain function that can manage common knowledge applicable to any environment and local knowledge reflecting its specific environment. Deep learning is effective for acquiring common knowledge because the performance of deep learning relies on the amounts of training and big training data that can be accessed for such knowledge; however, deep learning is ineffective for acquiring local knowledge because no big training data for such knowledge exist. Thus, we propose a brain-inspired learning model and system for acquiring local knowledge using small training data. We focus on the amygdala because its classical fear conditioning is effective for training using small training data. We propose an amygdala-inspired classical conditioning model comprising multiple self-organizing maps (lateral nucleus) and a fully connected neural network (central nucleus), imitating the function and structure of the amygdala. The proposed model is applied to a task of a waiter robot in a restaurant, and the model can learn customers’ preferences after only a few human-robot interactions. We accelerate the computation of the model and reduce its power consumption by proposing a hardware-oriented algorithm for the model and its digital hardware design and implement it in an XCZU9EG field programmable gate array. The hardware-oriented algorithm reduces the multiplication operations and exponential functions requiring huge hardware resources. The performance of the hardware operated at 150 MHz is 1,273 times faster than the software implementation on Arm Cortex-A53, and the power consumption of the chip is 5.009 W.