On-chip inductance modeling of VLSI interconnects
On-chip inductance modeling of VLSI interconnects
复制标题
VLSI 互连的片上电感建模
DOI：
10.1109/isscc.2000.839736
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
T. Young
中科院分区：
文献类型：
--
作者：
X. Qi;B. Kleveland;Zhiping Yu;S. Wong;R. Dutton;T. Young
在千兆赫兹频率下，长互连线表现出传输线行为。对于主要的信号和电源/地线，使用铜线和更宽的导线，感应阻抗(j/spl omega/L)可以与导线的电阻分量(R)相媲美。由于电感、延迟增大，产生过冲，电感串扰已不能再被忽略。最近在4 mm长的线上以0.25/splµ/m的工艺显示了诱导效应。给出了从该测试芯片中提取的典型时钟线的时延。当延迟是线路长度的线性函数时，RC延迟随线路长度的平方而增大。因此，对于中等长度的线路，诱导效应实际上更为突出。必须考虑中间长度母线和本地时钟的感应效应。随着技术规模的扩大，栅极延迟时间将继续减少，而短、低阻时钟线的延迟将保持不变。因此，对于逐渐变短的线路，感应效应将变得更加突出。文中模拟了电感对串扰的影响。当模拟中包含感应耦合时，可以观察到较大的耦合和振铃效应。目前，只考虑了几个全局时钟和母线的感应效应，这对未来的设计是不够的。虽然有3D电磁全波解算器可用，但它们无法管理当今集成电路的复杂性。为了对中长母线和本地时钟的电感效应进行建模，需要一个快速的自动电感提取和验证工具。
At gigahertz frequencies, long interconnect wires exhibit transmission line behavior. Using copper and wider wires for major signal and power/ground lines, inductive impedance (j/spl omega/L) could become comparable to the resistive component of the wire (R). Due to the inductance, delay increases, over-shoot occurs, and inductive crosstalk can no longer be ignored. Inductive effects were recently demonstrated in 4 mm-long lines in a 0.25 /spl mu/m process. The extracted delays of a typical clock line from this test chip are shown. While the delay is a linear function of line length, the RC delay increases with the square of the line length. As a result, the inductive effects are actually more prominent for lines with intermediate lengths. The inductive effects for the intermediate length buses as well as local clocks must be considered. As technology is scaled, the gate delay time will continue to be reduced while the delay of short, low-resistive clock lines will remain constant. The inductive effects will therefore become prominent for progressively short lines. The article shows simulated inductance effects on crosstalk. Larger coupling and ringing effects are observed when inductive coupling is included in the simulation. Currently, the inductive effects are only considered for a few global clocks and buses, which is insufficient for future designs. Although 3D electromagnetic full wave solvers are available, they cannot manage the complexity of today's integrated circuits. To model the inductive effects of intermediate-length buses as well as local clocks, a fast automated inductance extraction and verification tool is necessary.