A fault-tolerant ICAP controller with a selective-area soft error mitigation engine
A fault-tolerant ICAP controller with a selective-area soft error mitigation engine
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具有选择性区域软错误缓解引擎的容错 ICAP 控制器
DOI：
10.1109/ahs.2017.8046378
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
T. Arslan
中科院分区：
文献类型：
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作者：
A. Adetomi;Godwin Enemali;T. Arslan
动态部分重新配置(DPR)允许运行时访问现场可编程门阵列的配置存储器(CMEM)。依赖于DPR的一个关键功能是任务重新配置，其中电路在时间和空间上被多路复用，以减少设备数量和成本。此外，在任务关键型应用中，DPR用于软错误抑制(SEM)。这两个关键功能需要访问相同的CMEM接口，建议将更多时间(>；99%)分配给扫描电子显微镜，以实现持续的全器件可靠性。我们提出了一种带有完全集成的扫描电子显微镜引擎的容错控制器，该引擎允许对现场可编程门阵列进行选择性区域扫描，以便在不影响可靠性的情况下增加可用于重新配置的时间。一项来自NASA喷气推进实验室的成分红外成像光谱仪(CIRIS)仪器的案例研究表明，当只考虑CIRIS仪器的数据处理核心时，比Xilinx SEMIP节省高达74%的时间。
Dynamic partial reconfiguration (DPR) allows runtime access to the configuration memory (CMEM) of FPGAs. A key function that relies on DPR is task reconfiguration, where circuits are multiplexed in time and space in order to reduce device count and cost. Moreover, in mission-critical applications, DPR is used for soft error mitigation (SEM). These two key functions require access to the same CMEM interface and the recommendation is that more time (> 99%) should be allocated to SEM for continuous full-device reliability. We present a fault-tolerant controller with a fully integrated SEM engine that allows selective-area scanning of the FPGA in order to increase the time available for reconfiguration without compromising reliability. A case study drawn from the NASA JPL's Compositional InfraRed Imaging Spectrometer (CIRIS) instrument shows a time saving of up to 74% over the Xilinx SEM IP when only the data processing core of the CIRIS instrument is considered.