A robust architecture for post-silicon skew tuning
A robust architecture for post-silicon skew tuning
复制标题
用于硅后偏差调整的稳健架构
DOI：
10.1109/iccad.2011.6105417
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
Shih
中科院分区：
文献类型：
--
作者：
Mac Y. C. Kao;Kun;Shih
时钟偏差最小化是VLSI设计领域的重要内容。由于工艺、电压和温度（PVT）变化的存在，具有容忍PVT变化能力的后硅倾斜调谐（PST）技术引起了广泛的讨论。PST架构可以动态地最小化时钟偏差，甚至在芯片制造之后。然而，测试PST架构的容差能力是非常困难的，因为时钟偏差并不直接影响设计的功能。此外，在传统的测试环境中创建PVT变化并不容易。与以往大多数关注PST体系结构的实现和性能问题的工作不同，本文的目标是提出有效的测试机制并验证变异容忍能力。此外，我们还提出了一种新的结构，以增加PST体系结构在制造故障情况下的鲁棒性。我们的实验表明，在很少的开销下，我们可以实现鲁棒性。
Clock skew minimization is important in VLSI design field. Due to the presence of Process, Voltage, and Temperature (PVT) variations, the Post-Silicon Skew Tuning (PST) technique with the ability of tolerating PVT variations has brought a broad discussion. A PST architecture can dynamically minimize the clock skew even after a chip is manufactured. However, testing the variation tolerance ability of a PST architecture is very difficult because the clock skew does not directly affect the functionality of a design. In addition, creating PVT variation in the traditional testing environment is not easy. Unlike most previous works which focus on the implementation and the performance issues of a PST architecture, the objective of this paper is to propose efficient test mechanisms and verify the variation tolerance ability. In addition, we also propose a novel structure to increase the robustness of a PST architecture in case of a manufacturing fault. Our experiment shows that with little overhead, we can achieve robustness.