Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX
Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX
复制标题
DOI：
--
复制
发表时间：
2017-08
期刊：
影响因子：
--
通讯作者：
Craig Disselkoen;David Kohlbrenner;Leo Porter;D. Tullsen
中科院分区：
文献类型：
--
作者：
Craig Disselkoen;David Kohlbrenner;Leo Porter;D. Tullsen
级别的缓存（LLC）攻击通常在硬件中利用定时侧通道，因此很大程度上依靠计时器来进行此类侧面通道攻击。攻击绕过这些防御，不取决于其功能而不是定时渠道，Prime+中止了Intel TSX硬件服务器和消费者级处理器都表明，Prime+流产不仅对重要的防御类别，而且在精度和效率方面都超过了最先进的LLC Prime+Prime攻击检测速度（在每秒事件中）比英特尔Skylake架构上的LLC Prime+探针高3×，同时产生较少的假阳性。
Last-Level Cache (LLC) attacks typically exploit timing side channels in hardware, and thus rely heavily on timers for their operation. Many proposed defenses against such side-channel attacks capitalize on this reliance. This paper presents PRIME+ABORT, a new cache attack which bypasses these defenses by not depending on timers for its function. Instead of a timing side channel, PRIME+ABORT leverages the Intel TSX hardware widely available in both server- and consumer-grade processors. This work shows that PRIME+ABORT is not only invulnerable to important classes of defenses, it also outperforms state-of-the-art LLC PRIME+PROBE attacks in both accuracy and efficiency, having a maximum detection speed (in events per second) 3× higher than LLC PRIME+PROBE on Intel's Skylake architecture while producing fewer false positives.