FPGA Implementation of the Conjugate Gradient Method
FPGA Implementation of the Conjugate Gradient Method
复制标题
共轭梯度法的 FPGA 实现
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
A. Sergyienko
中科院分区：
文献类型：
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作者：
O. Maslennikov;V. Lepekha;A. Sergyienko
针对FPGA器件中的代数问题，提出了一种有理分式系统。分数由n位整数分子和n位整数分母组成，可以表示尾数为2n位的数。在FPGA器件上开发了实验线性方程组求解器，实现了递归共轭梯度法。其硬件运算单元可以在流水线模式下计算n=35的分数数的加、乘、除。建议的单元操作的频带矩阵的维数高达3500。
The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n -bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.