Voter insertion algorithms for FPGA designs using triple modular redundancy
Voter insertion algorithms for FPGA designs using triple modular redundancy
复制标题
使用三重模块化冗余的 FPGA 设计的选民插入算法
DOI：
10.1145/1723112.1723154
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
M. Wirthlin
中科院分区：
文献类型：
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作者：
Jonathan M. Johnson;M. Wirthlin
三重模块冗余（TMR）是一种常见的可靠性技术，用于减轻在辐射环境中工作的FPGA设计中的单粒子翻转（SEU）。对于采用配置清理的FPGA系统，在所有反馈路径中需要多数表决器，以确保TMR复制之间的正确同步。然而，同步表决器消耗额外的资源并影响系统时序。本文将介绍和对比四种在自动执行TMR时插入同步表决器的算法。面积成本和时间的影响，每个算法上的一些电路基准将报告。本文将证明，其中一个算法提供了最好的整体时序性能的结果，平均9.8%的关键路径长度增加了一个三重设计没有选民。另一种算法以略高的时间成本提供了更好的面积结果（比没有投票者的三重设计平均增加2.1%的面积）。
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast four algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be reported. This paper will demonstrate that one of the algorithms provides the best overall timing performance results with an average 9.8% increase in critical path length over a triplicated design without voters. Another algorithm provides far better area results at a slightly higher timing cost (an average 2.1% area increase over a triplicated design without voters).