A highly-parallel VLSI architecture for a list sphere detector
A highly-parallel VLSI architecture for a list sphere detector
复制标题
DOI：
10.1109/icc.2004.1313025
复制
发表时间：
2004-06
期刊：
影响因子：
--
通讯作者：
B. Widdup;G. Woodward;G. Knagge
中科院分区：
文献类型：
--
作者：
B. Widdup;G. Woodward;G. Knagge
在一个格子中寻找最近的点是一个NP难问题，我们需要一个简化的架构。此外，对于解码/检测问题，期望置信度测量或软信息的输出，然而生成这样的信息进一步使任务复杂化。本文提出了一种有效的和高度并行化的体系结构，特别适合于ASIC实现的列表球检测器。各种程度的并行性进行了探讨和比较。这种架构在多用户和MIMO检测器中找到应用，提供发送符号的软估计。
Finding the nearest point in a lattice is an NP-hard problem for which we desire a simplified architecture. Furthermore, output of confidence measures or soft information is desirable for decoding/detection problems, yet generating such information further complicates the task. This paper presents an efficient and highly parallelisable architecture for a list sphere detector that is particularly suited to ASIC implementation. Various degrees of parallelism are explored and compared. This architecture finds application in multiuser and MIMO detectors, providing soft estimates of the transmitted symbols.