Common path pessimism removal: An industry perspective: Special Session: Common Path Pessimism Removal
Common path pessimism removal: An industry perspective: Special Session: Common Path Pessimism Removal
复制标题
消除悲观主义的共同路径：行业视角：特别会议：消除悲观主义的共同路径
DOI：
10.1109/iccad.2014.7001412
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
V. Garg
中科院分区：
文献类型：
--
作者：
V. Garg
工艺参数，例如晶体管宽度，不仅在多个制造批次之间，而且在来自相同制造批次的相同管芯内可能有很大变化。除了工艺变化外，芯片的不同部分可能会有不同的电压和温度。这些工艺-电压-温度(PVT)变化被称为片上变化(OCV)，可能会非系统地影响布线和单元延迟。这种可变性是通过在静态定时分析(STA)期间将OCV降级添加到路径延迟来解释的，在STA中，原始定时值被分为早期(下限)和晚期(上界)量。然后针对这些新的延迟进行芯片计时，以确保芯片的安全运行。任何未知或难以建模的变化效应也可以在这些OCV降级中获得保证金。然而，这种额外的悲观情绪会显著增加实现定时关闭的难度，从而延长设计周期和上市时间。特别是，时钟网络上的过度悲观造成了最大的设计周期波动，因为悲观的时钟延迟几乎影响了所有的数据路径。本次会议从行业的角度讨论了公共路径悲观消除(CPPR)的概述和挑战，CPPR是从时钟路径安全地消除过度悲观的方法。
Process parameters, e.g., transistor width, may greatly vary not only across multiple manufacturing lots, but also within the same die from the same manufacturing lot. In addition to process variations different parts of a chip may see different voltages and temperatures. These process-voltage-temperature (PVT) variations are termed as On-Chip Variations (OCV) and can unsystematically affect wire and cell delays. This variability is accounted for by adding OCV de-ratings to path delays during static timing analysis (STA), where the original timing values are split into early (lowerbound) and late (upperbound) quantities. Chip timing is then done against these new delays to ensure safe chip operation. Any unknown or hard-to-model variation effect can also be margined for in these OCV de-ratings. However, this additional pessimism can significantly increase the difficulty to achieve timing closure, thereby elongating the design cycle and time to market. In particular, excess pessimism along clock network creates the most design-cycle churn, as pessimistic clock delays impact nearly all data paths. This session discusses the overview and challenges of common path pessimism removal (CPPR), the method of safely removing excess pessimism from clock paths, from an industry perspective.