A 14 b 100 Msample/s CMOS DAC designed for spectral performance
A 14 b 100 Msample/s CMOS DAC designed for spectral performance
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DOI：
10.1109/4.808897
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发表时间：
1999-02
期刊：
影响因子：
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通讯作者：
A. Bugeja;B. Song;P. Rakers;S. Gillig
中科院分区：
文献类型：
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作者：
A. Bugeja;B. Song;P. Rakers;S. Gillig
在60 MSample/s时，DAC SFDR对于5.1 MHz输入信号为80 dB，对于25.5 MHz输入信号仅降至75 dB。以前专用于此速度和分辨率的DAC仅在较低时钟和/或信号频率下才表现出类似的SFDR。该DAC采用0.8 /spl mu/m CMOS工艺（最小门长为0.65 /spl mu/m）实现，在100 MSample/s采样速率下功耗为750 mW，并采用特殊的输出级电路来获得动态性能。
At 60 MSample/s, DAC SFDR is 80 dB for 5.1 MHz input signals and is down only to 75 dB for 25.5 MHz input signals. Previous DACs specified for operation at this speed and resolution have exhibited similar SFDR only at lower clock and/or signal frequencies. The DAC is implemented in a 0.8 /spl mu/m CMOS process (minimum gate length is 0.65 /spl mu/m), consumes 750 mW at 100 MSample/s speed, and utilizes a special output stage circuit to obtain dynamic performance.