Thread-level speculation on off-the-shelf hardware transactional memory
Thread-level speculation on off-the-shelf hardware transactional memory
复制标题
对现成硬件事务内存的线程级推测
DOI：
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复制
发表时间：
2014
期刊：
影响因子：
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通讯作者：
T. Nakaike
中科院分区：
文献类型：
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作者：
Rei Odaira;T. Nakaike
线程级推测可以通过将单线程应用程序的执行分成多个任务并推测地在多个线程中执行这些任务来加快单线程应用程序的速度。高效的线程级推测需要硬件支持内存冲突检测、存储缓冲和执行回滚，此外，以前的研究还提出了高级优化设施，如有序事务和数据转发。最近，硬件事务性内存（HTM）的实现进入了市场，对线程级猜测的硬件支持很少。然而，很少有实现提供高级优化工具。因此，确定线程级推测在当前HTM实现上的实现程度，以及将来应该实现哪些优化工具是很重要的。在我们的研究中，我们研究了Intel TSX中现成HTM实现的线程级推测。为了线程级别的推测，我们在SPEC CPU2006中手动修改了潜在的并行基准测试。我们的实验结果表明，即使没有先进的优化设施，线程级别的推测也会导致高达11%的加速，但实际上在大多数情况下会降低性能。与我们的预期相反，性能损失的主要原因不是缺乏对有序事务的硬件支持，而是由于内存冲突导致的事务中止。我们的研究表明，未来的硬件不仅应该支持有序事务，还应该支持内存数据转发、数据同步、多版本缓存和用于线程级推测的字级冲突检测。
Thread-level speculation can speed up a single-thread application by splitting its execution into multiple tasks and speculatively executing those tasks in multiple threads. Efficient thread-level speculation requires hardware support for memory conflict detection, store buffering, and execution rollback, and in addition, previous research has also proposed advanced optimization facilities, such as ordered transactions and data forwarding. Recently, implementations of hardware transactional memory (HTM) are coming into the market with minimal hardware support for thread-level speculation. However, few implementations offer advanced optimization facilities. Thus, it is important to determine how well thread-level speculation can be realized on the current HTM implementations, and what optimization facilities should be implemented in the future. In our research, we studied thread-level speculation on the off-the-shelf HTM implementation in Intel TSX. We manually modified potentially parallel benchmarks in SPEC CPU2006 for thread-level speculation. Our experimental results showed that thread-level speculation resulted in up to an 11% speed-up even without the advanced optimization facilities, but actually degraded the performance in most cases. In contrast to our expectations, the main reason for the performance loss was not the lack of hardware support for ordered transactions but the transaction aborts due to memory conflicts. Our investigation suggests that future hardware should support not only ordered transactions but also memory data forwarding, data synchronization, multi-version cache, and word-level conflict detection for thread-level speculation.
利用主内存数据库中的硬件事务内存
DOI：
10.1109/icde.2014.6816683
发表时间：
2014
期刊：
2014 IEEE 30th International Conference on Data Engineering
影响因子：
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作者：
V. Leis;A. Kemper;T. Neumann
通讯作者：
T. Neumann
使用 Haswell 硬件事务内存探索垃圾回收
DOI：
10.1145/2602988.2602992
发表时间：
2014
期刊：
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影响因子：
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作者：
Ritson C
通讯作者：
Ritson C
使用英特尔® 事务同步扩展提高内存数据库索引性能
DOI：
10.1109/hpca.2014.6835957
发表时间：
2014
期刊：
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)
影响因子：
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作者：
T. Karnagel;R. Dementiev;R. Rajwar;K. Lai;T. Legler;B. Schlegel;W. Lehner
通讯作者：
W. Lehner